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FPGA  / ASIC Design Verification Engineers & Project Leaders

Location: Alabama & Arizona

FPGA / ASIC Design Verification Engineers & Project Leaders needed for a world leading developer of advanced wireless communications systems. Company has an established reputation for excellence, and provides a technically challenging and rewarding environment - offering a wide variety of in-depth projects and technology applications.

Locations: Engineering Centers situated in Alabama and Arizona

Positions range from Senior and Principal Engineer to Project Leader

Compensation: $120 - 160K, depending upon experience level. Full relocation is provided.


• SystemVerilog/OVM, Vera or Specman, UVM or AVM
• Experience in functional verification , test benches, constrained random or  assertions
• Experience in IC design verification going full cycle with designs
• Environments: Standard Cell ASIC's or mixed signal IC , FPGA's or analog mixed signal