ASIC Design Verification Engineers
Location: New York City
ASIC Design Verification Engineers needed for a leading developer of revolutionary high-performance, proprietary electronic systems.
Company provides a dynamic and highly creative work environment, with ultra modern facilities, deep R&D resources, and a setting that enables exploration into a wide variety of new technologies.
Compensation and benefits are extremely generous. Full relocation is also provided.
Minimum BSEE (or relevant technical degree) and 5 to 10+ years of experience with large, complex high-performance chips (1 GHz or above, many millions of gates, large die sizes). Skills with methodologies and tools including:
• System Verilog CRV
• OVM, VMM, or UVM
• Synopsys VCS, Mentor Questa, or Cadence Incisive
• Knowledgeable with CDC, linting, DRC, Spyglass, DFT, low-power emulation, verification IP
• Scripting ability with Perl, Python, and/or Tcl; experience with C++ is a plus
• Strong communication skills
This is a unique chance to expand your skills and your career in a dynamic and creative work environment, and participate in the evolution of new technologies.